Design of an Oscillator with Low Phase Noise and Medium Output Power in a 0.25 μm GaN-on-SiC HEMT Technology

To investigate the effects of both the drain and gate bias voltages on the performance of GaN HEMT oscillator, a 0.25 μm GaN-on-SiC HEMT oscillator is presented in this paper. Utilizing the designed oscillator, the trade-off between phase noise and output power is effectively investigated at the circuit level. As a result, the designed oscillator can provide low phase noise and medium output power simultaneously. The phase noise at VGS = -2.3 V and VDS = 3.3 V is measured to be -112 dBc/Hz and -143 dBc/Hz at 100 kHz offset and 1 MHz offset respectively from a 4.954 GHz carrier, with an output power of more than 14 dBm. Moreover, the output power can be boosted to 26 dBm, if a drain bias 16 V is used, while good phase noise of -132 dBc/Hz @ 1 MHz is still achievable. The achieved phase noise is low among all reported GaN HEMT oscillators. This work has successfully demonstrated that the monolithic oscillator fabricated in GaN-on-SiC HEMT technology features low phase noise as well as medium output power simultaneously. Index Terms GaN-on-SiC, high electron-mobility transistor (HEMT), integrated oscillator and ultra-low noise. This research was supported by the National Research Foundation Singapore through the Singapore MIT Alliance for Research and Technology (SMART)'s Low Energy Electronic Systems (LEES) research programme. The authors are with the VIRTUS, School of Electrical Electronic Engineering, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). Design of an Oscillator with Low Phase Noise and Medium Output Power in a 0.25 μm GaN-on-SiC HEMT Technology Hang Liu ([email protected]), Xi Zhu ([email protected]), Chirn Chye Boon ([email protected]), Xiang Yi ([email protected])